Markdown

Run the 0.0 Edit questions.md task (Click the VSCode Tasks icon on the side bar () and then the task’s name).

Many of our remaining assignments will include some questions in a “MarkDown” (.md) file. Markdown is a common markup language and can be used to create formatted text files using only basic text. Replace the TODO line following the Q1.1 line as described in questions.md.

Review how to create lists in MarkDown and complete Q1.2.

As a Markup language, MarkDown is really meant to create a web-friendly view of the text with additional styling. Preview your questions.md with the styling by opening the MarkDown Preview. On macOS this is done with Command+shift+V (macOS) or Control+shift+V (Windows). Note that your cursor has to be in the .md text window and the window has to be active.

Review other features of MarkDown MarkDown and answer Q1.3

Full Adder: Revisited

Recall that a “full adder” does the general purpose addition needed for multi-digit numbers: it adds two addends and a carry-in.

Run Task 2.1 (Simulate fulladder.sv). Does is add correctly? Explain your findings in Q2.1

Wiki Wisdom

Wikipedia provides one common boolean algebra equation for a full adder, that combines $A$, $B$, and $C_{in}$ to product a sum, $S$, and carry, $C_{out}$:

$$S = A \oplus B \oplus C_{in} $$ $$C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B)) $$

Does the depicted circuit match these equations? Explain any discrepencies in Q2.2.1

Use task 2.2 (Edit fulladder.sv) to edit the SystemVerilog model for the full adder (.sv for a SystemVerilog file). Review the code and confirm that it matches the equations given or correct it if needed. If you make changes, see if they impact your tests from part 2.1. (It may help to review Verilog operators. The author’s slides for our text include a summary as do the course slides)

Make mistakes

Experiment to see how the environment behaves when there’s a single syntax error in the file (wrong symbols, missing punctuation, misspellings, etc. ). Repeat with a few different types of error. Answer Q2.3.1

(That is, make a single mistake, wait a few seconds to try to observe an issue, undo it and repeat with a different error)

Errors may not be shown in ways that you have experienced in other tools. Watch the Problems tab for problems, but be aware that there can be delays before it updates and it can occasionally be out-of-sync with your work.

Make more than one mistake at a time and Answer Q2.3.2

Re-run the Simulation task with one or more errors. What happens? Try a few variations and report your findings in Q2.3.3

Undo all errors and return the fulladder to a working, correct implementation.

Test Benches

Run the fulladder testbench task, which will run a test file meant to confirm the fulladder works. Answer Q2.4.1.

If they run correctly (indpendend of whether parts behave correctly), testbenches will open their results in a waveform viewer panel where you can select devices (Scopes) and signals within the devices (Variables) to examine. Experiment with the waveform view of the testbench and determine how the inputs, a, b, and cin, change over time. Explain your findings via Q2.4.2.

Structure & Verilog

The prior model was a behavioral model of a full adder. Now use tasks 3.1-3.3 to complete a structural model of the full adder by precisely describing the parts and connections between parts. As before, a partial implementation has already been provided.

Primitive gates can be modeled with the format: type(output, inputs...). For example, a 3-input or gate could be modeled with or(output, a, b, c); or with a unique name for the instance of the or gate, like or gate1(out, a, b, c);.

Complete Q3.1

Hardware and Synthesis

The hardware kit comes with an UPduino, which includes a Field-Programmable Gate Array. This is essentially a device that contains many digital logic devices that can perform complex functiosn (the “Gate Array”) and can be reconfigured (reprogrammed in the field).

We will be:

1. Using the Codespace to “synthesize” a hardware-description language model of a digital device to a format called a bitstream. The “synthesis” process will take your work in Verilog files and figure out how to represent it on the programmable parts in the UPduino. The bitstream that’s created is the blueprint for how the UPduino’s internal parts need to be configure.
2. The Codespace can’t interact directly with your UPduino, but a browser with WebUSB support, like Chrome or Edge, can. The Codespace will launch a new webpage that will open in your web browser. That page will be used to send the bitstream to your UPduino.

Follow the directions in FPGA Programming to light the green LED on the UPduino

Follow the directions in FPGA Programming to configure the LED & Key board and test it

Use Task 4.3 to test your behavioral fulladder on the hardware! It will use buttons, LEDs, and displays as follows:

Please be aware that many boards have bad LEDs, which should be marked on the board. Consequently, the corresponding LEDs may not ever turn on when a button is pressed but the 7-segment displays should still behave correctly.