Extra Credit! [Optional]

This extra credit homework is meant to allow you to summarize things you’ve learned about digital logic, and/or have fun going a little further, and/or overcome any prior setbacks. It is eligible for up to 2.5% overall extra credit (2.5% of the overall grade: About 74% of an entire homework and more than a studio or reading and equal to a studio lead). The actual credit obtained depends on the effort and breadth/depth of your work.

This is a creative, open-ended assignment. The intent is to demonstrate a functional ability to work with concepts from modules 1-7, with some emphasis on basic digital logic (modules 1-5).

Requirements and Credit

Due Date

Late Work Not Accepted!

As this is optional / extra and partial work is eligible for some partial credit, late work will not be accepted.


When/if in doubt, submit partial work early.

All work should be completed by 11:59pm on Wed, Dec. 3rd (pushed to Gradescope) and demos completed by 4pm on Friday, Dec. 12th.

Scope

  1. It needs be a moderate, new digital logic creation (i.e., your work and non-trivial).
  2. It needs to be reasonably distinct from prior course work. For example, a simple state machine that is comparable to the washer may be eligible for some credit, but probably not the full 2.5% unless there are substantial additions. (I.e., derivative works are a way to get some additional experience with Digital Logic, but not worth full credit!)
  3. It needs to run on the FPGA hardware.

Submission

  1. You need to give a demo to either Professor Hall or Professor Siever. (Live, in-person strongly preferred. Zoom-based demos will be allowed to compensate for prior travel plans that make in-person demos impossible)
  2. The final work needs to be submitted/committed to Gradescope.
  3. You need to complete the usual questions.md in the repo to summarize your work.

Examples

  1. Games

    Pong, the first commercially successful video game, was built directly from digital logic. Although using 8, 7-segment displays and 8 buttons is a bit limited, you may be able to come up with some interesting games.

  2. An new CPU!

    The AVR microcontroller commonly sued in Arduinos was a student project (story here). You don’t have to develop anything nearly as complex as the RISC-V (or AVR), but a processor with a 4-10 instructions to do a combination of data manipulation, data movement, and control, is sufficient.

  3. Other ????

    We’re open to other digital logic creations, including some things that interface to external hardware. However, please open a private post on Piazza (instructors or just Profs. Hall & Siever) to discuss other ideas. Please have your idea reviewed/approved before starting on it, especially if you are attaching hardware!

    Caution!

    Any interfacing with external hardware will need to get pre-approval to be accepted. Generally things that use low power interfaces will be accepted without issue, but we may require additional detail for anything that could pose risk (e.g., high power/current).

Resources

The link to create a repo: link

  • Files & Folders: An overview of how files and folders are used to create projects.

Overview / Container Demo

Minor updates and additions to the video:

  • CSE 2600 is using a custom fork of “Tasks in Sidebar” that will (now) automatically reload when the tasks are rebuild. (There’s no longer a Reload Tasks button in the list of tasks because it’s done automatically when one does Rebuild Tasks)
  • The repo’s common folder includes a few modules:
    • ledandkey.sv is the I/O board support. It provides inputs for the buttons and outputs for each segment/LED. This is used in Homework 4A, 4B, 5, and 7A.
    • spinner.sv will do the “spinner” effect on a single 7-segment display. It was used in Homework 4B. It uses the ledandkey module.
    • digit_select.sv uses two buttons and a 7-segment display to allow users to select a nibble value (increase and decrease the displayed value). This was used in homework 5 (ALU project) to select values for testing. It also uses the ledandkey module.
    • timed_enable.sv this module allows one to “reduce” a clock to a slower clock. This was used in Homework 5 to slow the 6MHz clock to a rate that was reasonable to simultate the wash cycles.
    • pins.pcf specifies how names, like tm_clock, in the top most module are connected to the outside world (i.e., which pin they should connect to). It was present in all homeworks.

For each of the above you can look in the top.sv file of prior assignments to get a sense of how they may be used.

Submission

Be sure to commit/push all work, including a completed questions.md, to Gradescope (via GitHub).